1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to systems and methods of probe testing semiconductor chips.
2. Description of the Related Art
Current integrated circuits routinely include many tens or even hundreds of millions of transistors and other circuit devices configured in arrangements of staggering complexity. Not surprisingly, testing of integrated circuits is vital to ensure that both the huge numbers of circuit devices and the myriad of manufacturing steps required to make those devices meet or exceed design specifications. One type of electrical test routinely performed on integrated circuits is performed at the wafer level and involves establishing ohmic contact with certain areas of an integrated circuit using a special instrument known as a probe system. After ohmic contact is established, the tester of the probe system electrically stimulates the integrated circuit in a variety of ways to test various functionalities thereof. Another type of testing for chips destined for packages is performed after the individual chips are diced from the wafer and mounted into packages.
A conventional probe system consists of a prober, which is an instrument designed to hold a semiconductor wafer and step it to various positions so that the individual dice thereof can be brought into selected contact with a tester, which is another instrument that typically performs the actual electrical stimulation of the individual dice. In one conventional set up, a probe card is mounted to the prober and used to establish the ohmic contact with the semiconductor wafer. The probe card consists of a stack of a printed circuit board, a semiconductor chip package substrate, and a probe head. The printed circuit board holds the probe substrate and is configured to perform a relatively low-speed testing on the integrated circuits of the semiconductor wafer. The probe substrate is similar in design to a semiconductor chip package substrate. The probe substrate typically includes a collection of conductor pins that project away from the substrate and are used to establish the ohmic contact with areas on the semiconductor dice of the wafer.
One conventional variant of a probe substrate includes an array of pins that are capable of contacting not only peripheral areas of an integrated circuit but also internal areas, such as solder bumps in the case of a flip-chip type integrated circuit. Another conventional variant of a probe substrate includes two or more collections of conductor pins that are typically configured to contact peripheral, but not internal areas of an integrated circuit. The conventional single array probe substrate is limited to probing a single semiconductor die at a time. The conventional dual site probe substrate is capable of multi-site probing, but only for peripheral areas of an integrated circuit.
An additional drawback of conventional probe systems is the low-speed capabilities of the conventional probe stack printed circuit board. Thus, at the wafer test level, only relatively low speed tests may be performed. High-speed tests that can identify additional types of faults and defects that will render a given die as scrap, must await final package testing. Thus, there are often instances where one or more dice on a semiconductor wafer have defects that remain latent during wafer level testing only to be revealed during final test after packaging. In those instances, otherwise defective dice nevertheless undergo dicing, packaging and package level testing before such defects are discovered. If yield limiting defects can be discovered earlier in the fabrication cycle, manufacturing and testing costs can be lowered.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.